Field of the Invention
The present invention generally relates to a semiconductor device. Priority is claimed on Japanese Patent Application No. 2010-184131, filed Aug. 19, 2010, the content of which is incorporated herein by reference.
Description of the Related Art
Semiconductor devices with a dummy wiring which is disposed at the edge part of a memory cell block have been generally known. The dummy wiring is formed to suppress the influence of sparseness and concentration of wirings. For example, in the memory cell block, there is usually a plurality of bit lines that are disposed repeatedly, forming a microfine pattern. If a dummy bit line is formed further to the outside from a bit line disposed at the outermost column of the memory cell block, it is possible to form the shape of the bit lines disposed in the outermost column with the same high precision as the shape of the other bit lines.
Japanese Unexamined Patent Application, First Publication, No. JP-A-2007-250020 discloses a semiconductor memory device as an example of a conventional semiconductor device having dummy wirings. Japanese Unexamined Patent Application, First Publication, No. JP-A-2007-250020 discloses the semiconductor memory device having a dummy word line that selects a first dummy cell group, and a dummy bit line on which data of the first dummy cell group is transferred. The dummy bit lines (DBLs) disclosed in Japanese Unexamined Patent Application, First Publication, No. JP-A-2007-250020 have an electrical potential that varies in response to potential control of a dummy word line (DWL).
With the shrinking of the size of semiconductor devices, investigations are being done regarding semiconductor devices including transistors with a structure having a small surface area, such as vertically structured transistors. In the vertically structured transistor, rather than the three electrodes of the transistor (source, gate, and drain) being arranged in the planar direction of the semiconductor substrate, they are arranged perpendicularly with respect to the semiconductor substrate, so that the surface area of the transistor can be made small.
For example, Japanese Unexamined Patent Application, First Publication, No. JP-A-2009-81377 discloses a semiconductor device in which a plurality of transistor rows made of a plurality of prismatic vertical MOS transistors that share a gate of a first type of conductivity are disposed and formed into an array configuration.
Japanese Unexamined Patent Application, First Publication, No. JP-A-2003-22684 discloses a nonvolatile semiconductor memory device that includes a third main bit line that supplies an electrical potential that is substantially the same potential as the drain potential to a sub-bit line that neighbors a sub-bit line that is the drain side of a selected memory cell.
Japanese patent, No. JP-B-3512833 discloses a nonvolatile semiconductor memory device including a data resetting means. The data resetting means looks for a bit line having a current leakage fault after data is loaded to a data circuit. Of the data in the data circuit, the data resetting means resets only the data corresponding to the faulty bit line.